This invention relates to a semiconductor memory device and a manufacturing method thereof and more particularly to a semiconductor memory device including memory cell units (NAND cells, AND cells, DINOR cells and the like) each consturcted by connecting a plurality of memory cells having conductive bodies of booster plates and a method for manufacturing the same.
Conventionally, an electrically rewritable EEPROM is known as one of the semiconductor memory devices. Among them, a NAND type EEPROM having NAND strings each constructed by serially connecting a plurality of memory cells receives much attention because it can be formed with high integration density.
The NAND type EEPROM is disclosed in K, -D. Suh et al., xe2x80x9cA 3.3V 32Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme,xe2x80x9d IEEE J. Solid-State Circuits. vol. 30, pp. 1149-1156, November 1995 (document 1 ) and Y. Iwata et al., xe2x80x9cA 35 ns Cycle Time 3.3V Only 32Mb NAND Flash EEPROM,xe2x80x9d IEEE J. Solid-State Circuits, vol. 30, pp. 1157-1164, November 1995 (document 2).
In the program operation of the EEPROM disclosed in the above documents, the channel potential of a program inhibition NAND string in the selected block is determined by the capacitive coupling between the word line and the channel. Therefore, in order to set the program inhibition voltage to a sufficiently high voltage, it is important to sufficiently effect the initial charging operation of the channel and set the capacitive coupling ratio between the word line and the channel to a relatively large value.
The capacitive coupling ratio B between the word line and the channel is calculated by the following equation.
B=Cox/(Cox+Cj)
where Cox is the total sum of the gate capacitances between the word line and the channel and Cj is the total sum of junction capacitances of the source and drain of a cell transistor.
On page 1153 of the document 1, it is described that the coupling ratio is 80%, but in order to obtain this value, it is necessary to reduce the junction capacitance Cj to xc2xc of that of the conventional case, for example. However, in order to reduce the junction capacitance, the impurity concentration of a P well must be made low or the impurity concentrations of the source and drain of the cell transistor must be made low. If the impurity concentration of the P well is lowered, the field withstand voltage between memory cells will be lowered, and therefore, there is a limitation in lowering the impurity concentration. Further, if the impurity concentrations of the source and drain of the cell transistor are lowered, the resistances of the source and drain are increased, thereby causing a cell current to be reduced.
Therefore, as a method for increasing the gate capacitance Cox and reducing the junction capacitance Cj, there is proposed a method for setting the word line pitch to 2F when the design rule is set to F, and as a result, reducing the space between the adjacent word lines to reduce the junction capacitance Cj as is disclosed in a document by R. Shiorta et al., xe2x80x9cA 2.3 xcexcm2 Memory Cell Structure for 16Mb NAND EEPROMs,xe2x80x9d in IEDM""90 Technical Digest, pp. 103-106. December 1990 (document 3).
However, in this method, since two mask members are used when the word line is etched, there occurs a problem that misalignment occurs between a silicon nitride film (SiN) which is the first mask member and a resist which is the second mask member. Therefore, a problem relating to the process occurs and the manufacturing yield is lowered. Further, two processing masks for word lines are required and the manufacturing process becomes complicated and the manufacturing cost is made high.
Further, a method for reducing the junction capacitance Cj by negatively biasing the P well at the time of program to expand the depletion layer of the junction capacitance is provided. However, the junction capacitance is approximately inversely proportional to the reciprocal of the square root of the sum of the built-in potential of the junction and the reverse bias. Therefore, even if xe2x88x922V is applied to the P well with respect to the channel potential of 6V, for example, the junction capacitance is reduced to only approx. 90% and a significant effect cannot be expected. Further, an additional circuit, power and time for applying a negative bias to the P well are required.
As described above, various methods for increasing the coupling ratio B are proposed, but each method has the problem as described above.
In the document 2 and Tanaka et al., xe2x80x9cA Quick Intelligent Program Architecture for 3V-Only NAND-EEPROM""s,xe2x80x9d in Symp. VSLI Circuits Dig. Tech. Papers, June 1992, pp. 20-21 (document 4), the channel potential of the program inhibition NAND string at the time of program is applied in a manner different from that of the document 1. That is, in the document 1, the channel potential is raised by use of the capacitive coupling between the word line and the channel set in the electricaly floating state, but in the document 2 and document 4, a program inhibition voltage raised by the charge pump of the peripheral circuit in the chip is directly applied to the channel from the sense amplifier via the bit line.
As the problem of the EEPROM described in the document 2 and document 4, the following two problems are given. First, since the program inhibition voltage is supplied from the sense amplifier to the bit line, it is necessary to form the transistors constituting the sense amplifier by use of high breakdown voltage transistors on the design condition of the sense amplifier.
When the power supply voltage Vcc is 3.3V, a transistor applied with the voltage Vcc can be designed as a transistor which has a thin gate oxide film having a film thickness of 120 angstrom, for example, and has a short gate length. That is, the transistor can be designed by use of the severe design rule of 0.4 xcexcm, for example.
However, if the program inhibition voltage is set at 8V, it is required to design a transistor which can withstand the voltage as a transistor having a thick gate oxide film with a film thickness of 200 angstrom, for example, and has a long gate length of 1 xcexcm. That is, it is necessary to design the transistor with the relatively large design rule of 1 xcexcm, for example. Therefore, the layout area of the sense amplifier is increased and it is difficult to arrange the sense amplifier in the narrow bit line pitch.
As the second problem, it becomes necessary to apply a high voltage to a selected gate line and non-selected word line which correspond to pass transistors by taking the threshold voltages thereof into consideration in order to input the program inhibition voltage to the channel via the bit line. Application of a high voltage to the non-selected word line causes a problem that the non-selected cell of the NAND string to be programmed is erroneously programmed. Therefore, in the document 2 and document 4, the program inhibition voltage is limited to such a potential which does not cause the erroneous programming and there occurs a problem that the permissible potential width (window) of the program inhibition voltage is narrowed.
Further, if a high voltage is applied to the selected gate line, a strong electric field is applied to the gate oxide film of the NAND string to be programmed since the channel potential of the NAND string to be programmed is Vss (0V), and there occurs a problem that the gate oxide film of the selected gate transistor will be broken.
As the measure for coping with the above problems, recently, a NAND type EEPROM in which the channel potential of a non-programming NAND string is set high by use of conductive bodies of booster plates and the program/erase/read voltage is lowered is proposed. The NAND type EEPROM having the booster plates is disclosed in a document by J. D. Choi et al., xe2x80x9cA Novel Booster Plate Technology in High Density NAND Flash Memories for Voltage Scaling-Down and Zero Program Disturbance,xe2x80x9d in Symp. VLSI Technology Dig. Tech. Papers, June 1996, pp. 238-239 (document 5).
The NAND type EEPROM having the booster plates has two advantages. The first advantage is that the capacitive coupling xcex3 at the time of program becomes large. In the NAND type EEPROM having no booster plate, the capacitive coupling xcex3 is expressed by the following equation.
xcex3=Ccf/(Cfs+Ccf)
where Ccf is a capacitance between the control gate (word line) and the floating gate and Cfs is a capacitance between the floating gate and the substrate. The capacitive coupling xcex3b of the NAND type EEPROM having the booster plates is expressed by the following equation.
xcex3b=(Ccf+Cbf)/(Cfs+Ccf+Cbf)
where Cbf is a capacitance between the booster plate and the floating gate. Thus, the capacitive coupling xcex3b is larger than the capacitive coupling xcex3 in a case where no booster plate is used. Therefore, the program voltage at the time of program can be lowered.
Since the capacitive coupling ratio at the time of erase is expressed by (1xe2x88x92xcex3b), the potential difference between the substrate and the floating gate can be made large and it is possible to attain a high speed erase operation or lower the erase voltage in comparison with a case where no booster plate is used. Further, if xcex3b is increased, a voltage applied to the pass transistor at the read time can be lowered.
The second advantage is that the capacitive coupling ratio between the control gate (word line) and the channel becomes larger. The capacitive coupling ratio Bb in a case where the booster plates are used is expressed by the following equation.
Bb=(Cox+Cboot)/(Cox+Cboot+Cj)
where Cox is the total sum of gate capacitances between the control gate (word line) and the channel, Cboot is the total sum of gate capacitances between the booster plate and the channel and Cj is the total sum of junction capacitances of the source and drain of the cell transistor. Therefore, even if the voltage of the pass transistor is not excessively raised at the time of program, the channel potential of the program inhibition NAND string can be raised and the margin against the erroneous programming can be increased.
In the NAND type EEPROM described in the document 5, the capacitance Cbf between the booster plate and the floating gate is determined by the area of the side wall of the floating gate. Therefore, in order to further increase the capacitance Cbf, it is necessary to increase the film thickness of the floating gate to make the side wall high, reduce the film thickness of the plate oxide film lying between the side wall of the floating gate and the booster plate, or increase the dielectric constant of a material of the plate oxide film.
However, if the film thickness of the floating gate is increased, a difference in level in the floating gate becomes larger, making it difficult to effect the succeeding process. Further, if the film thickness of the plate oxide film is reduced or a material with the high dielectric constant is used as the plate oxide film, there is a limitation in the reliability. Therefore, in the NAND type EEPROM described in the document 5, it is difficult to further increase the capacitance Cbf and lower the program, erase, read voltages.
Further, in the NAND type EEPROM described in the document 5, since the ion-implantation into the source/drain regions of the cell transistors of the NAND string is effected after the control gates (word lines) are formed, there occurs a problem that the coupling ratio between the control gate (word line) and the channel is made smaller by the junction capacitance Cj.
An object of this invention is to provide a semiconductor memory device capable of increasing the capacitance between the booster plate and the floating gate the effecting the program/erase/read operations at a low voltage and a method for manufacturing the same. Further, an object of this invention is to provide a semiconductor memory device and a method for manufacturing the same in which the junction capacitance of the channel portion of the memory cell is made small and the capacitive coupling ratio between the control gate and the channel is increased so as to enhance the program inhibition voltage at the time of program and enlarge the margin against the erroneous programming, thereby making it possible to enhance the reliability.
In order to attain the above object, a semiconductor memory device according to this invention comprises a conductive body formed on a semiconductor substrate; a floating gate insulatively formed on the conductive body with an insulating film disposed therebetween, a capacitor being formed between the floating gate and part of the upper surface and the side wall of the conductive body; and a control gate insulatively formed on the floating gate with gate insulating film disposed therebetween.
According to the semiconductor memory device with the above structure, a capacitance between the booster plate (conductive body) and the floating gate can be increased. As a result, the program/erase/read operations can be effected at a low voltage.
Further, a semiconductor memory device according to this invention comprises conductive bodies formed on a semiconductor substrate; floating gates insulatively formed on the conductive bodies with an insulating film disposed therebetween, capacitors being each formed between the floating gate and at least part of the upper surface of the conductive body; control gates insulatively formed on the floating gates with an insulating film disposed therebetween; and at least one memory cell unit including a plurality of memory cell transistors each of which includes a corresponding one of the floating gates and a corresponding one of the control gates.
According to the semiconductor memory device with the above structure, a capacitance between the booster plate (conductive body) and the following gate can be increased. As a result, the program/erase/read operation can be effected at a low voltage.
In above semiconductor memory device, regions of the semiconductor substrate which lie below the conductive body and the floating gate have the same conductivity type.
With the semiconductor memory device of the above structure, since a diffusion layer having a different conductivity type from that of the channel portion is not formed in the region of the semiconductor substrate which lies directly below the booster plate (conductive body), the junction capacitance of the channel portion of the memory cell can be made small and the capacitive coupling ratio between the control gate and the channel portion can be increased. As a result, the program inhibition voltage at the time of program can be enhanced and the margin against the erroneous programming can be enlarged.
Further, a method for manufacturing a semiconductor memory device having memory cells according to this invention comprises the steps of forming a first insulating film on a semiconductor substrate; forming a first conductive film on the first insulating film; patterning the first conductive film in a linear form along the wiring direction of control gates of the memory cells; forming a second insulating film on the first conductive films linearly patterned; insulatively forming floating gates on part of the upper surfaces and the side surfaces of the first conductive films with the second insulating film disposed therebetween; forming third insulating films on the floating gates; and forming control gates on the third insulating films.
According to the method for manufacturing the semiconductor memory device having the above steps, a semiconductor memory device having memory cells in each of which a capacitance between the booster plate (conductive body) and the floating gate can be increased can be manufactured.
Further, a method for manufacturing a semiconductor memory device having at least one memory cell unit including a plurality of memory cells according to this invention comprises the steps of forming element isolation regions on a semiconductor substrate; forming a first insulating film on the semiconductor substrate; forming a first conductive film on the first insulating film; patterning the first conductive film into a plurality of linear portions along the control gate line direction of the memory cells; forming a second insulating film on the first conductive films patterned into the linear portions; forming a second conductive film on the second insulating film; forming isolation trenches in the second conductive film above the element isolation regions which are adjacent in the control gate line direction of the memory cells; forming a third insulating film on the second conductive film; forming a third conductive film on the third insulating film; patterning the third conductive film, third insulating film and second conductive film in a self-alignment manner to form control gate lines formed of the third conductive film and floating gates formed of the second conductive film at least between the first conductive films which are adjacent to each other; and forming diffusion layers in a self alignment manner in regions acting as source/drain regions of the at least one memory cell unit by ion-implantation by use of the first conductive films patterned into the linear portions and the control gate lines.
According to the method for manufacturing the semiconductor memory device having the above steps, a semiconductor memory device having at least one memory cell unit in which a capacitance between the booster plate (conductive body) and the floating gate can be increased can be manufactured. Further, according to the manufacturing method, since a diffusion layer having a different conductivity type from that of the channel portion is not formed in the region of the semiconductor substrate which lies directly below the booster plate (conductive body), a semiconductor memory device having at least one memory cell unit in which the junction capacitance of the channel portion of each memory cell can be made small and the capacitive coupling ratio between the control gate and the channel portion can be increased can be manufactured.
Further, a method for manufacturing a semiconductor memory device having memory cells according to this invention comprises the steps of forming a first insulating film on a semiconductor substrate; forming a first conductive film on the first insulating film; forming a second conductive film on the first conductive film; patterning the second and first conductive films in a linear form along the wiring direction of control gates of the memory cells; forming a second insulating film on laminated bodies of the second and first conductive films linearly patterned; insulatively forming floating gates on part of the upper surfaces and the side surfaces of the laminated bodies of the second and first conductive films with the second insulating film disposed therebetween; forming third insulating films on the floating gates; and forming control gates on the third insulating films.
According to the method for manufacturing the semiconductor memory device having the above steps, a semiconductor memory device having memory cells in each of which a capacitance between the booster plate (conductive body) and the floating gate can be increased can be manufactured.
Further, a method for manufacturing a semiconductor memory device having at least one memory cell unit including a plurality of memory cells according to this invention comprises the steps of forming a first insulating film on a semiconductor substrate; forming a first conductive film on the first insulating film; patterning the first conductive film into a present pattern and forming element isolation trenches in the semiconductor substrate with the preset pattern used as a mask; filling an insulating material into the element isolation trenches to form element isolation regions; forming a second conductive film on the semiconductor substrate; patterning the second and first conductive films into a plurality of linear portions along the wiring direction of control gates of the memory cells; forming a second insulating film on laminated bodies of the second and first conductive films patterned into the linear portions; forming a third conductive film on the second insulating film; forming isolation trenches in the third conductive film above the element isolation regions which are adjacent in the control gate line direction of the memory cells; forming a third insulating film on the third conductive film; forming a fourth conductive film on the third insulating film; patterning the fourth conductive film, third insulating film and third conductive film in a self-alignment manner to form control gate lines formed of the fourth conductive film and floating gates formed of the third conductive film at least between the laminated bodies of the second and first conductive films; and forming diffusion layers in a self-alignment manner in regions acting as source/drain regions of the at least one memory cell unit by ion-implantation by use of the laminated bodies of the second and first conductive films patterned into the linear portions and the control gate lines.
According to the method for manufacturing the semiconductor memory device having the above steps, a semiconductor memory device having at least one memory cell unit in which a capacitance between the booster plate (conductive body) and the floating gate can be increased can be manufactured. Further, according to the manufacturing method, since a diffusion layer having a different conductivity type from that of the channel portion is not formed in the region of the semiconductor substrate which lies directly below the booster plate (conductive body), a semiconductor memory device having at least one memory cell unit in which the junction capacitance of the channel portion of the memory cell can be made small and the capacitive coupling ratio between the control gate and the channel portion can be increased can be manufactured.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.